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Eagle – Board Review

Posted: September 27th, 2010 | Author: | Filed under: Uncategorized | Tags: | 1 Comment »

Before I discovered Cadsoft EAGLE, I  used to use <gasp> ExpressPCB’s free CAD tools to make my own boards. One of the cool features that software has is the ability to sequentially step through all the netlists implied by your schematic highlighting the associated traces on your PCB.  This was super useful in reviewing layout  for “connectedness.” I recently posted to an Eagle forum inquiring about whether anyone knew of a way to achieve this capability in Eagle. I was pleasantly surprised when someone posted the following ULP code that works like a charm!

if (board) board(B) {
UL_SIGNAL nextsignal;
int match = 0;
string s;
B.signals(S) {
if (match != 0) {
    nextsignal = S;
match = 2;
break;
}
if (argc <= 1) {
nextsignal = S;
match = 2;
break;
} else {
if (argv[1] == S.name) {
match = 1;
}
}
} /* next signal */

sprintf(s,”match = %d, for %s”, match, argv[1]);
status(s);
if (match != 2) {
dlgMessageBox(“No more signals”);
exit(“assign C+N ‘run showsigs’;”);
}

sprintf(s, “Next signal \”%s\””, nextsignal.name);
sprintf(s,”assign C+N ‘run showsigs %s;’; show ‘%s’”,
nextsignal.name, nextsignal.name);
exit(s);
}

Just save it to the ulp directory under your Eagle installation as something like “showsigs.ulp” and run it, using Ctrl-N to step through your signals one at a time. This is a great way to catch “silly” errors in your layout. Hope it helps you as much as it’s helped me!